15, 16, 17 These protection schemes can be categorized into two types: current limiting and voltage limiting. Various gate over-voltage protection techniques have long been developed for FETs. 12, 13, 14 Although power FETs are designed to sustain large drain bias, they are equally vulnerable to the forward gate overstress. A large over-voltage gate stress can easily result in severe threshold voltage instabilities 8, 9, 10, 11 or even lead to long-term degradation (e.g., breakdown) of the gate dielectric or semiconductor barrier layer between the gate and the channel. 6, 7 Despite the above advantages and broad applications, the voltage-driven FETs have a drawback of being very susceptible to the overloaded gate voltage. 1, 2, 3, 4, 5, 6, 7 These applications include low-power FETs in logic and analog IC’s for high-speed computing and IoT, 4, 5 HEMTs/MISFETs based on compound semiconductors (e.g., GaN, SiC) for high-power and high-frequency switchings. The demonstrated semiconducting gate as over-voltage protection for HEMT can be extended to other FETs, which can become another advantageous arena for the possible applications of the layered two-dimensional materials.įield-effect transistor (FET), as a voltage-driven device with large input impedance, is at the heart of modern semiconductor technologies (e.g., CMOS, TFT, compound semiconductor HEMT, etc.) supporting a wide range of existing and emerging applications. In implementing the semiconducting gate, the layered two-dimensional materials such as the adopted MoS 2 have several important benefits such as the feasibility of high-quality crystals on different gate dielectrics and the good controllability of semiconducting gate depletion threshold voltage by the layer thickness. Furthermore, the self-adjustable semiconducting gate potential with drain bias can even boost the ON-current while guaranteeing the safe operation of FET. Most importantly, the proposed semiconducting gate can deliver inherent over-voltage protection for field-effect transistors (FETs). The MoS 2 semiconducting gate can effectively turn on and turn off the HEMT without sacrificing the subthreshold swing and breakdown voltage. The SG-FET is demonstrated on an AlGaN/GaN high-electron mobility transistor (HEMT) by adopting single-layer MoS 2 as the gate electrode. A semiconducting gate field-effect transistor (SG-FET) structure based on 2D/3D heterostructures is proposed here. Various 2D/3D heterostructures can be created by harnessing the advantages of both the layered two-dimensional semiconductors and bulk materials.
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